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Job Description

The Timing and Communication Group (TCG) at Microchip is actively seeking an analog design engineer. The responsibility spans wide range of activities such as the design, simulation and validation of analog integrated circuits (ICs). The products are usually mixed signal SOC designs.

The Analog team develops the critical IP blocks used in the TCG timing products. These circuits include multi-GHz PLL circuits, high speed digital circuits, MEMS drivers and high-speed performance IO pads.

As an Analog Design Engineer and as part of the Analog IP team the individual will:

• Work with analog design lead and architects to design specific analog IP blocks
• Simulate analog circuits across process corners and operating conditions
• Models design blocks to be included on top level mixed signal simulations
• Block level validation of process silicon devices and system level lab evaluation
  

Requirements/Qualifications

• Bachelor's or master’s degree in Electrical Engineering
• Minimum 5 years’ experience as an IC layout designer using deep submicron CMOS process technology
• Knowledge of chip level integration and ESD concepts is a plus
• Knowledge in scripting using SKILL language, Perl and TCL is a plus
• Strong knowledge in Cadence IC layout flow and tools
• Familiar with Innovus, is a plus
• Experience in layout verification and debugging such as DRC, ERC, LVS, ANTENNA DRC
• Floor planning from sub-block to chip top level
• Very good understanding of matching techniques
• Knowledge in TCL, Perl, Python and/or SKILL languages is a plus
• Good communication, teamwork skills and experience working with multi-site team desirable